Conventionally, there is a composite type semiconductor memory in which a flash memory (32 M bit capacity) and a static random access memory (NOR (4 M bit capacity) are integrally sealed in a fine pitch ball grid array (FBGA) package using a stack chip. Address input terminals and data input/output terminals are commonly used in the flash memory and the NOR for the input/output electrodes of the FBGA package. However, the control terminals thereof are independently provided (For example, “COMPOSITE MEMORY (STACKED CSP) FLASH MEMORY+RAM DATA SHEET” MODEL NAME: LRS1380, [ONLINE] on Dec. 10, 2001 SHARP CORPORATION [RETRIEVAL DATE: Aug. 21, 2002] (Non-Patent Document 1).
There is also a composite type semiconductor memory in which a flash memory chip and a DRAM chip are integrally sealed in a lead frame type package. In this composite type semiconductor memory, the flash memory and the DRAM have common address input terminals, data input/output terminals, and control terminals for the input/output electrodes of the package, through which data are inputted and outputted (for example, FIG. 1 and FIG. 15 of Japanese Patent Application Laid-Open Publication No. 5-299616 (Patent Document 1) and EP Patent No. 0566306 (Patent Document 2)).
There is also a system composed of a flash memory operated as a main memory, a cache memory, a controller and a CPU (for example, FIG. 1 of Japanese Patent Application Laid-Open Publication No. 7-146820 (Patent Document 3)).
There is also a semiconductor memory composed of a flash memory, a DRAM, and a transfer control circuit (for example, FIG. 2 of Japanese Patent Application Laid-Open Publication No. 2001-5723 (Patent Document 4) and Japanese Patent Application Laid-Open Publication No. 2002-366429 (Patent Document 5)).